Cisco hiring ASIC Design Verification Engineer in San Jose, CA
Cisco Jasper
Salary not disclosed
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This appears to be a continuously recycled listing
No hiring manager or recruiter is identified for this role
The job description is unusually short
2 more things we noticed -- upgrade to see them
Missing key information you'd need to make a decision
No salary listed. You could waste 3 interviews before finding out.
Some verification signals are missing
Vague description — hard to know what you'd actually do
Recently refreshed — someone's actively managing this
Employer quality signals are concerning
Job Description
Knowledge of formal verification tools (e.g., Jasper or VC Formal); Experience with RTL Design desirable; Familiarity with ASIC/SoC design flow.
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View Cisco Jasper ProfileThis assessment is generated algorithmically from publicly available job listing data. It does not constitute legal advice, an accusation of fraud, or a definitive determination of hiring intent. Updated daily.